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Verilog: NAND Gate Behavioral Modelling with Testbench Code
Verilog Code NAND Gate Behavioral Modelling module NAND_GATE ( input a, b, output out ); reg out; always @(a or b) begin if (a==1 & b==1) out = 1’b0; else out = 1’b1; endmodule //test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, out=%b”, a, b, out); end endmodule Xilinx Output: NAND Gate Verilog Code Behavioral Modelling
Verilog: AND Gate Behavioral Modelling with Testbench Code
Verilog Code AND Gate Behavioral Modelling module AND_GATE ( input a, b, output out ); reg out; always @(a or b) begin if (a==1 & b==1) out = 1’b1; else out = 1’b0; endmodule //test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, out=%b”, a, b, out); end endmodule Xilinx Output: AND Gate Behavioral Response
Barcode Generator Tool Free
Free Generate Barcode using Javascript and HTML: Barcode Generator tool is an innovative tool to generate different types of barcodes. This tool made using Javascript, CSS and HTML. An ultimate tool to generate different type of barcodes. An interesting aspect of using this tool is that this tool can work even in offline mode. As javascript and css files are integrated inside HTML itself. You can generate different types of barcodes. Change the foreground and background colors, change the font style, change the font color, vary the size to barcode, size of font, etc. An interesting tool for javascript enthusiastic. Download the source code from the below given button and start exploring different types of barcodes !! Watch Youtube Tutorial Video: Watch the Youtube video to see how the settings work, and feel free to modify the code. This is just the beta version, tasks to do: Implement a javascript to save the barcode on your computer. Barcode is generated in "svg" format.
Verilog: OR Gate Behavioral Modelling with Testbench Code
Verilog Code OR Gate Behavioral Modelling module OR_GATE ( input a, b, output out ); reg out; always @(a or b) begin if (a==0 & b==0) out = 1’b0; else out = 1’b1; endmodule //test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; #100 a=1; b=0; #100 a=1; b=1; end initial begin #100 $ monitor (“a=%b, b=%b, out=%b”, a, b, out); end endmodule Xilinx Output: OR Gate Response
Applied Instrumentation GTU (Sem-1) - ME Instrumentation and Control (IC)
1. STUDY MATERIAL for Applied Instrumentation GTU (Sem-1) - ME Instrumentation and Control (IC) SEM 1: Subjects: AIDC (Advanced Industrial Drives and Control) ISC (Intelligent Systems and Control) OTE (Optimization Techniques for Engineers) ESI (Embedded System for Instrumentation) IPR Click on the below given links to download study material: Syllabus Books Notes Study Material Lab Manual Question Papers Assignments Sem 2: ME - Applied Instrumentation Click on the below given link to download study material: Sem 2 Folder Subjects: AVD (Advanced Verilog Design) ISI (Intelligent Sensors and Instrumentation) DC (Digital Control) ASPE (Advanced Signal Processing and Estimation) Disaster Management Also See: Optimization Techniques in C Verilog Programming Filter Designing
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VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench
Verilog Code for Full Subtractor Structural/Gate Level Modelling module full_sub(borrow,diff,a,b,c); output borrow,diff; input a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of Verilog Programming
VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin // Initialize Inputs a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s0=0;s1=1;a=0;b=1;c=0;d=0; #100; s0=1;s1=0;a=0;b=0;c=1;d=0;
VLSI: Half Subtractor and Full Subtractor Gate Level Modelling
Half Subtractor: Verilog Module Code: module half_subtractor ( input a, input b, output diff output borr ); wire x; xor (diff,a,b); not (x,a); and (borr,x,b); endmodule Full Subtractor: Verilog Module Code: module full_subtractor ( input a, input b, input c, output diff output borr ); wire x,n2,z,n1; xor s1(x,a,b); not s3(n2,x); not s4(n1,c); and s5(y,n1,b); xor s2(diff,a,x); and s6(z,n2,a); or (borr,y,z); endmodule
VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100;