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C Program for Level Sketch
C Level Sketch: #include<stdio.h> #include<conio.h> #include<math.h> int main() { float th,ov, HH,H,L,LL,lowTap,UpTap,CC,HH1,H1,L1,LL1,HHper,Hper,Lper,LLper,BtTap; char ch; do { printf("\nEnter Tank Height in mm:"); scanf("%f",&th); printf("\nHeight of HH:"); scanf("%f",&HH); printf("\nHeight of H:"); scanf("%f",&H); printf("\nHeight of L:"); scanf("%f",&L); printf("\nHeight of LL:"); scanf("%f",&LL); printf("\nEnter Height of Overflow Nozzle (if required):"); scanf("%f",&ov); if (ov != 0) { th = ov; } else { th = th; } printf("Height Valid: %.2f",th); HHper = (HH * 100)/th; Hper = (H * 100)/th; Lper = (L * 100)/th; LLper = (LL * 100)/th; if (HHper < 90 && LLper > 10) { printf("\nAlarm Positions are Valid."); } else { printf("\nCha
Sun - The Ball of Fire
Mysterious Sun: Electromagnetic winds emmited from Sun are solar winds. Solar winds consists of protons and electrons, when these protons and electrons interact with Earth's magnetic field sky get lit up by different colors. The solar winds are emmited by solar holes in sun, as these solar holes are less dense than other parts of Sun, they provide path to allow the wind outwards to surface of Sun. These winds are thrown out by such a huge force that they can travel very long distances, even reaching to Earth. These winds can have speed up to 1000 Km/sec. Solar Emission Even though we know Sun from centuries, there are many mysteries of Sun remained unsolved. Most popular mystery is regarding Corona of Sun. Corona is outer layer of Sun's atmosphere. Corona is hotter than the inner layer Chromosphere. Sun's visible surface Photosphere has temperature 5800°C. Outer layer of Photosphere is Chromosphere. Temperature of Chromosphere is estimated to be 4000°C. B
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VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench
Verilog Code for Full Subtractor Structural/Gate Level Modelling module full_sub(borrow,diff,a,b,c); output borrow,diff; input a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of Verilog Programming
VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin // Initialize Inputs a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; s0=0;s1=1;a=0;b=1;c=0;d=0; #100; s0=1;s1=0;a=0;b=0;c=1;d=0;
VLSI: Half Subtractor and Full Subtractor Gate Level Modelling
Half Subtractor: Verilog Module Code: module half_subtractor ( input a, input b, output diff output borr ); wire x; xor (diff,a,b); not (x,a); and (borr,x,b); endmodule Full Subtractor: Verilog Module Code: module full_subtractor ( input a, input b, input c, output diff output borr ); wire x,n2,z,n1; xor s1(x,a,b); not s3(n2,x); not s4(n1,c); and s5(y,n1,b); xor s2(diff,a,x); and s6(z,n2,a); or (borr,y,z); endmodule
1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench
Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d = 1;s0 = 1;s1 = 0; #100;d = 1;s0 = 0;s1 = 1; #100;d = 1;s0 = 1;s1 = 1; end Output: Verilog 1-4 DEMUX Verilog Code Response Other Verilog Programs: Go to Index of Verilog Programming