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C Program for Level Sketch
C Level Sketch: #include<stdio.h> #include<conio.h> #include<math.h> int main() { float th,ov, HH,H,L,LL,lowTap,UpTap,CC,HH1,H1,L1,LL1,HHper,Hper,Lper,LLper,BtTap; char ch; do { printf("\nEnter Tank Height in mm:"); scanf("%f",&th); printf("\nHeight of HH:"); scanf("%f",&HH); printf("\nHeight of H:"); scanf("%f",&H); printf("\nHeight of L:"); scanf("%f",&L); printf("\nHeight of LL:"); scanf("%f",&LL); printf("\nEnter Height of Overflow Nozzle (if required):"); scanf("%f",&ov); if (ov != 0) { th = ov; } else { th = th; } printf("Height Valid: %.2f",th); HHper = (HH * 100)/th; Hper = (H * 100)/th; Lper = (L * 100)/th; LLper = (LL * 100)/th; if (HHper < 90 && LLper > 10) { ...
Sun - The Ball of Fire
Mysterious Sun: Electromagnetic winds emmited from Sun are solar winds. Solar winds consists of protons and electrons, when these protons and electrons interact with Earth's magnetic field sky get lit up by different colors. The solar winds are emmited by solar holes in sun, as these solar holes are less dense than other parts of Sun, they provide path to allow the wind outwards to surface of Sun. These winds are thrown out by such a huge force that they can travel very long distances, even reaching to Earth. These winds can have speed up to 1000 Km/sec. Solar Emission Even though we know Sun from centuries, there are many mysteries of Sun remained unsolved. Most popular mystery is regarding Corona of Sun. Corona is outer layer of Sun's atmosphere. Corona is hotter than the inner layer Chromosphere. Sun's visible surface Photosphere has temperature 5800°C. Outer layer of Photosphere is Chromosphere. Temperature of Chromosphere is estimated to be 4000°C....
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VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs ...
Verilog: 2 - 4 Decoder Structural/Gate Level Modelling with Testbench
Verilog Code for 2-4 Decoder Structural/Gate Level Modelling 2-4 Line Decoder module decoder_2_to_4( input a0, input a1, output d0, output d1, output d2, output d3 ); not (an0,a0),(an1,a1); and (d0,an0,an1),(d1,a0,an1),(d2,an0,a1),(d3,a0,a1); endmodule //Testbench code for 2-4 Decoder Structural/Gate Level Modelling initial begin // Initialize Inputs a0 = 0;a1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a0=1;a1=0; #100; a0=0;a1=1; #100; a0=1;a1=1; end Output: Verilog 2-4 Decoder Response Other Verilog Programs: Go to Index of Verilog Prog...
Verilog: 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code
Verilog Code for 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code module 4_2_ENC( input [3:0]din, output [1:0]dout ); reg [1:0]dout; always @ (din) case (din) 1 : dout[0] = 0; 2 : dout[1] = 1; 4 : dout[2] = 2; 8 : dout[3] = 3; default : dout = 2’bxx; endcase endmodule //Testbench code for 4 to 2 Encoder Behavioral Modelling using Case Statement initial begin // Initialize Inputs din = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; din=1; #100; din=2; #100; din=4; #100; din=8; end initial begin #100 $monitor (“ din=%b, dout=%b”, din, dout); end endmodule Xillinx Output: 4 - 2 Encoder Behavioral Modelling Verilog Response
VLSI: 2 Bit Magnitude Comparator Dataflow Modelling
module mag_comp2bit( input a0, input a1, input b0, input b1, output p, // p = (a < b) output r, // r = (a > b) output q // q = (a = b) ); assign q = ((~a1) ^ (b1)) & (a0 & b0); assign p = (((~a1) & b1) | (b0 & (~a0) & (~a1)) | ((~a0) & b1 & b0)); assign r = ((a1 & (~b1)) | ((~b0) & a1 & a0) | (a0 & (~b1) & (~b0))); endmodule