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Verilog: 4 Bit Counter Behavioral Modelling using If Else Statement
Verilog Code for 4 Bit Counter Behavioral Modelling using If Else Statement module 4_bit_Count( input clock, reset, output [3:0]dout ); reg [3:0]dout; initial dout = 0; always @ (posedge (clock)) begin if (reset) dout <= 0; else dout <= dout + 1; end endmodule Xillinx Output: 4 Bit Counter Behavioral Modelling Response Also See: List of Verilog Programs
Verilog: Full Adder Behavioral Modelling with Testbench Code
Verilog Code Full Adder Behavioral Modelling module Full_Adder ( input a, b, cin; output sum, carry ); always @(a or b or cin) assign {carry,sum} = a + b + cin; endmodule // test-bench initial begin a=0; b=0; #100; //wait 100ns for global reset to finish //add stimulus here #100 a=0; b=1; cin=1; #100 a=1; b=0; cin=1; #100 a=1; b=1; cin=1; end initial begin #100 $ monitor (“a=%b, b=%b, cin=%b, sum=%b, carry=%b”, a, b, cin, sum, carry); end endmodule Xilinx Output: Verilog code for Full Adder Behavioral Modelling
Verilog Code for Gray to Binary Dataflow Modelling
Verilog Code for Gray to Binary Dataflow Modelling module gray_to_binary( input g0, input g1, input g2, input g3, output b0, output b1, output b2, output b3 ); assign b0 = g0;buf(b0,g0); assign b1 = g0 ^ g1; assign b2 = g0 ^ g1 ^ g2; assign b3 = g0 ^ g1 ^ g2 ^ g3; endmodule //Testbench code for Gray to Binary Dataflow Modelling initial begin ...
VLSI: 2-4 Decoder Dataflow Modelling with Testbench
Verilog Code for 2-4 Decoder Dataflow Modelling module decoder_2_to_4( input a0, input a1, output d0, output d1, output d2, output d3 ); assign an0 = ~ a0; assign an1 = ~ a1; assign d0 = an0 & an1; assign d1 = a0 & an1; assign d2 = an0 & a1; assign d3 = a0 & a1; endmodule //Testbench code for 2-4 Decoder Dataflow Modelling initial begin ...
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VLSI: BCD to Excess 3 and Excess 3 to BCD Dataflow Modelling
module bcd_ex3_Dataflow( input a, input b, input c, input d, output w, output x, output y, output z ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd( input w, input x, input y, input z, output a, output b, output c, output d ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule
VLSI: 1-4 DEMUX (Demultiplexer) Dataflow Modelling with Testbench
Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin // Initialize Inputs ...
VLSI: 4-1 MUX Dataflow Modelling with Testbench
Verilog Code for 4-1 MUX Dataflow Modelling module m41(out, i0, i1, i2, i3, s0, s1); output out; input i0, i1, i2, i3, s0, s1; assign y0 = (i0 & (~s0) & (~s1)); assign y1 = (i1 & (~s0) & s1); assign y2 = (i2 & s0 & (~s1)); assign y3 = (i3 & s0 & s1); assign out = (y0 | y1 | y2 | y3); endmodule //Testbench code for 4-1 MUX Dataflow Modelling initial begin // Initialize Inputs a = 1;b = 0;c = 0;d = 0;s0 = 0;s1 = 0; ...
1 to 4 DEMUX (Demultiplexer) Verilog CodeStructural/Gate Level Modelling with Testbench
Verilog Code for 1 to 4 DEMUX Structural/Gate Level Modelling 1-4 DEMUX module demux_1_to_4( input d, input s0, input s1, output y0, output y1, output y2, output y3 ); not(s1n,s1),(s0n,s0); and(y0,d,s0n,s1n),(y1,d,s0,s1n),(y2,d,s0n,s1),(y3,d,s0,s1); endmodule //Testbench code for 1 to 4 DEMUX Structural/Gate Level Modelling initial begin // Initialize Inputs d = 1; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100;d = 1;s0 = 1;s1 = 0; #100;d = 1;s0 = ...
Full Subtractor Verilog Code in Structural/Gate Level Modelling with Testbench
Verilog Code for Full Subtractor Structural/Gate Level Modelling module full_sub(borrow,diff,a,b,c); output borrow,diff; input a,b,c; wire w1,w4,w5,w6; xor (diff,a,b,c); not n1(w1,a); and a1(w4,w1,b); and a2(w5,w1,c); and a3(w6,b,c); or o1(borrow,w4,w5,w6); endmodule //Testbench code for Full Subtractor Structural/Gate Level Modelling initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a = 0;b = 0;c = 1; #100; a = 0;b = 1;c = 0; #100; a = 0;b = 1;c = 1; #100; a = 1;b = 0;c = 0; #100; a = 1;b = 0;c = 1; #100; a = 1;b = 1;c = 0; #100; a = 1;b = 1;c = 1; end Output: RTL Schematic: Full Subtractor Verilog Other Verilog Programs: Go to Index of Verilog Programming