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Verilog: SR Flip Flop Behavioral Modelling using If Else Statement with Testbench Code

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Verilog Code for SR Flip Flop Behavioral Modelling using If Else with Testbench Code

module SR_FF(
    input s,r,clock,reset,
    output q, qb
    );
reg q, qb; 

always @ (posedge (clock))
    begin  
        if (reset)
            begin
               q <= 0;
               qb <=1;
            end    
        else
            begin
               if (s != R)
                    begin
                    q <= s;
                    qb <= R;
                    end 
               else if (s == 1 && r == 1) 
                    begin 
                    q <= 1'bZ; 
                    qb <= 1'bZ; 
                    end 
            end
 
end   
endmodule
//Testbench code for SR Flip Flop Behavioral Modelling using If Else Statement
initial begin
// Initialize Inputs 
s = 0;r = 0; clock = 0; reset = 0;
// Wait 100 ns for global reset to finish 
#100;
// Add stimulus here 
#100; s=0; r=1; clock=1; reset=0; 
#100; s=1; r=0; clock=0; reset=1; 
#100; s=1; r=1; clock=1; reset=0;  
end
initial begin 
#100 
$monitor(“clock=%b, reset=%b, S=%b, R=%b, q=%b, qb=%b”,
clock, reset, s, r, q, qb); 
end 
endmodule

Xillinx Output:

Verilog Code for SR Flip Flop Behavioral Modelling with Testbench Code
SR Flip Flop Behavioral Modelling Response

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