Stellar Coding - Verilog, Filter Design and more..

module bcd_ex3_Dataflow(     input a,     input b,     input c,     input d,     output w,     output x,     output y,     output z     ); assign w = (a | (b & c) | (b & d)); assign x = (((~b) & c) | ((~b) & d) | (b & (~c) & (~d))); assign y = ((c & d) | ((~c) & (~d))); assign z = ~d; endmodule Excess 3 to BCD: module ex3_to_bcd(     input w,     input x,     input y,     input z,     output a,     output b,     output c,     output d     ); assign a = ((w & x) | (w & y & z)); assign b = (((~x) & (~y)) | ((~x) & (~z)) | (x & y & z)); assign c = (((~y) & z) | (y & (~z))); assign d = ~z; endmodule

Verilog Code for 1-4 DEMUX Dataflow Modelling module demux_1_to_4(     input d,     input s0,     input s1,     output y0,     output y1,     output y2,     output y3     ); assign s1n = ~ s1; assign s0n = ~ s0; assign y0 = d& s0n & s1n; assign y1 = d & s0 & s1n; assign y2 = d & s0n & s1; assign y3 = d & s0 & s1; endmodule //Testbench code for 1-4 DEMUX Dataflow Modelling initial begin                              // Initialize Inputs ...

Verilog Code for 2-4 Decoder Structural/Gate Level Modelling 2-4 Line Decoder module  decoder_2_to_4(      input  a0,      input  a1,      output  d0,      output  d1,      output  d2,      output  d3     );                 not (an0,a0),(an1,a1);                 and (d0,an0,an1),(d1,a0,an1),(d2,an0,a1),(d3,a0,a1); endmodule //Testbench code for 2-4 Decoder Structural/Gate Level Modelling initial  begin // Initialize Inputs a0 = 0;a1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here #100; a0=1;a1=0; #100; a0=0;a1=1; #100; a0=1;a1=1; end Output: Verilog 2-4 Decoder Response Other Verilog Programs: Go to Index of  Verilog Prog...

Verilog Code for 4 to 2 Encoder Behavioral Modelling using Case Statement with Testbench Code module 4_2_ENC(      input [3:0]din,      output [1:0]dout      ); reg [1:0]dout; always @ (din) case (din)     1 : dout[0] = 0;      2 : dout[1] = 1;      4 : dout[2] = 2;      8 : dout[3] = 3;       default : dout = 2’bxx; endcase endmodule //Testbench code for 4 to 2 Encoder Behavioral Modelling using Case Statement initial  begin // Initialize Inputs   din = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here   #100; din=1;  #100; din=2;  #100; din=4;  #100; din=8; end initial begin  #100   $monitor (“ din=%b, dout=%b”, din, dout);  end  endmodule Xillinx Output: 4 - 2 Encoder Behavioral Modelling Verilog Response

module mag_comp2bit(     input a0,     input a1,     input b0,     input b1,     output p,   // p = (a < b)     output r,     // r = (a > b)     output q     // q = (a = b)     ); assign q = ((~a1) ^ (b1)) & (a0 & b0); assign p = (((~a1) & b1) | (b0 & (~a0) & (~a1)) | ((~a0) & b1 & b0)); assign r = ((a1 & (~b1)) | ((~b0) & a1 & a0) | (a0 & (~b1) & (~b0))); endmodule